- CONFIG_VTI=n by default.
- Reorganize code such that the changes to cp_patch files are minimized
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Arun Sharma <arun.sharma@intel.com>
428b9f38XgwHchZEpOzRtWfz0agFNQ xen/include/asm-ia64/vmx_vcpu.h
428b9f38tDTTJbkoONcAB9ODP8CiVg xen/include/asm-ia64/vmx_vpd.h
428b9f38_o0U5uJqmxZf_bqi6_PqVw xen/include/asm-ia64/vtm.h
+428e120a-H-bqn10zOlnhlzlVEuW8A xen/include/asm-ia64/xenprocessor.h
421098b7LfwIHQ2lRYWhO4ruEXqIuQ xen/include/asm-ia64/xenserial.h
+428e120esS-Tp1mX5VoUrsGJDNY_ow xen/include/asm-ia64/xensystem.h
40715b2dWe0tDhx9LkLXzTQkvD49RA xen/include/asm-x86/acpi.h
3ddb79c3l4IiQtf6MS2jIzcd-hJS8g xen/include/asm-x86/apic.h
3ddb79c3QJYWr8LLGdonLbWmNb9pQQ xen/include/asm-x86/apicdef.h
########################################
# ia64-specific definitions
-CONFIG_VTI ?= y
+CONFIG_VTI ?= n
ifneq ($(COMPILE_ARCH),$(TARGET_ARCH))
CROSS_COMPILE ?= /usr/local/sp_env/v2.2.5/i686/bin/ia64-unknown-linux-
endif
pte_val(pfn_pte(__pa(my_cpu_data) >> PAGE_SHIFT, PAGE_KERNEL)),
PERCPU_PAGE_SHIFT);
-#ifdef CONFIG_VTI
- {
- u64 base;
- extern void vmx_switch_rr7(void);
-
- base = (u64) &vmx_switch_rr7;
- base = *((u64*)base);
- ia64_itr(0x1, IA64_TR_RR7_SWITCH_STUB, XEN_RR7_SWITCH_STUB,
- pte_val(pfn_pte(__pa(base) >> PAGE_SHIFT, PAGE_KERNEL)),
- RR7_SWITCH_SHIFT);
- printk("Add TR mapping for rr7 switch stub, with physical: 0x%lx\n", (u64)(__pa(base)));
- }
-#endif // CONFIG_VTI
-
ia64_set_psr(psr);
ia64_srlz_i();
---- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/page.h 2005-03-01 23:37:48.000000000 -0800
-+++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/page.h 2005-05-18 12:40:50.000000000 -0700
-@@ -32,6 +32,10 @@
+--- /home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/page.h 2005-03-01 23:37:48.000000000 -0800
++++ /home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/page.h 2005-05-20 09:36:02.000000000 -0700
+@@ -32,6 +32,7 @@
#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
#define PERCPU_PAGE_SHIFT 16 /* log2() of max. size of per-CPU area */
-+#ifdef CONFIG_VTI
-+#define RR7_SWITCH_SHIFT 12 /* 4k enough */
-+#endif // CONFIG_VTI
+
#define PERCPU_PAGE_SIZE (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
#define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */
-@@ -95,9 +99,15 @@
+@@ -95,9 +96,15 @@
#endif
#ifndef CONFIG_DISCONTIGMEM
#else
extern struct page *vmem_map;
extern unsigned long max_low_pfn;
-@@ -109,6 +119,11 @@
+@@ -109,6 +116,11 @@
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
typedef union ia64_va {
struct {
unsigned long off : 61; /* intra-region offset */
-@@ -124,8 +139,23 @@
+@@ -124,8 +136,23 @@
* expressed in this way to ensure they result in a single "dep"
* instruction.
*/
#define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
#define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;})
-@@ -197,7 +227,11 @@
+@@ -197,7 +224,11 @@
# define __pgprot(x) (x)
#endif /* !STRICT_MM_TYPECHECKS */
---- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/processor.h 2005-03-01 23:37:58.000000000 -0800
-+++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/processor.h 2005-05-18 12:40:50.000000000 -0700
-@@ -131,9 +131,166 @@
- __u64 ri : 2;
- __u64 ed : 1;
+--- /home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/processor.h 2005-03-01 23:37:58.000000000 -0800
++++ /home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/processor.h 2005-05-20 09:36:02.000000000 -0700
+@@ -94,7 +94,11 @@
+ #ifdef CONFIG_NUMA
+ #include <asm/nodedata.h>
+ #endif
++#ifdef XEN
++#include <asm/xenprocessor.h>
++#endif
+
++#ifndef XEN
+ /* like above but expressed as bitfields for more efficient access: */
+ struct ia64_psr {
+ __u64 reserved0 : 1;
+@@ -133,6 +137,7 @@
__u64 bn : 1;
-+#ifdef CONFIG_VTI
-+ __u64 ia : 1;
-+ __u64 vm : 1;
-+ __u64 reserved5 : 17;
-+#else // CONFIG_VTI
__u64 reserved4 : 19;
-+#endif // CONFIG_VTI
};
++#endif
-+#ifdef CONFIG_VTI
-+/* vmx like above but expressed as bitfields for more efficient access: */
-+typedef union{
-+ __u64 val;
-+ struct{
-+ __u64 reserved0 : 1;
-+ __u64 be : 1;
-+ __u64 up : 1;
-+ __u64 ac : 1;
-+ __u64 mfl : 1;
-+ __u64 mfh : 1;
-+ __u64 reserved1 : 7;
-+ __u64 ic : 1;
-+ __u64 i : 1;
-+ __u64 pk : 1;
-+ __u64 reserved2 : 1;
-+ __u64 dt : 1;
-+ __u64 dfl : 1;
-+ __u64 dfh : 1;
-+ __u64 sp : 1;
-+ __u64 pp : 1;
-+ __u64 di : 1;
-+ __u64 si : 1;
-+ __u64 db : 1;
-+ __u64 lp : 1;
-+ __u64 tb : 1;
-+ __u64 rt : 1;
-+ __u64 reserved3 : 4;
-+ __u64 cpl : 2;
-+ __u64 is : 1;
-+ __u64 mc : 1;
-+ __u64 it : 1;
-+ __u64 id : 1;
-+ __u64 da : 1;
-+ __u64 dd : 1;
-+ __u64 ss : 1;
-+ __u64 ri : 2;
-+ __u64 ed : 1;
-+ __u64 bn : 1;
-+ __u64 reserved4 : 19;
-+ };
-+} IA64_PSR;
-+
-+typedef union {
-+ __u64 val;
-+ struct {
-+ __u64 code : 16;
-+ __u64 vector : 8;
-+ __u64 reserved1 : 8;
-+ __u64 x : 1;
-+ __u64 w : 1;
-+ __u64 r : 1;
-+ __u64 na : 1;
-+ __u64 sp : 1;
-+ __u64 rs : 1;
-+ __u64 ir : 1;
-+ __u64 ni : 1;
-+ __u64 so : 1;
-+ __u64 ei : 2;
-+ __u64 ed : 1;
-+ __u64 reserved2 : 20;
-+ };
-+} ISR;
-+
-+
-+typedef union {
-+ __u64 val;
-+ struct {
-+ __u64 ve : 1;
-+ __u64 reserved0 : 1;
-+ __u64 size : 6;
-+ __u64 vf : 1;
-+ __u64 reserved1 : 6;
-+ __u64 base : 49;
-+ };
-+} PTA;
-+
-+typedef union {
-+ __u64 val;
-+ struct {
-+ __u64 rv : 16;
-+ __u64 eid : 8;
-+ __u64 id : 8;
-+ __u64 ig : 32;
-+ };
-+} LID;
-+
-+typedef union{
-+ __u64 val;
-+ struct {
-+ __u64 rv : 3;
-+ __u64 ir : 1;
-+ __u64 eid : 8;
-+ __u64 id : 8;
-+ __u64 ib_base : 44;
-+ };
-+} ipi_a_t;
-+
-+typedef union{
-+ __u64 val;
-+ struct {
-+ __u64 vector : 8;
-+ __u64 dm : 3;
-+ __u64 ig : 53;
-+ };
-+} ipi_d_t;
-+
-+
-+#define IA64_ISR_CODE_MASK0 0xf
-+#define IA64_UNIMPL_DADDR_FAULT 0x30
-+#define IA64_UNIMPL_IADDR_TRAP 0x10
-+#define IA64_RESERVED_REG_FAULT 0x30
-+#define IA64_REG_NAT_CONSUMPTION_FAULT 0x10
-+#define IA64_NAT_CONSUMPTION_FAULT 0x20
-+#define IA64_PRIV_OP_FAULT 0x10
-+
-+/* indirect register type */
-+enum {
-+ IA64_CPUID, /* cpuid */
-+ IA64_DBR, /* dbr */
-+ IA64_IBR, /* ibr */
-+ IA64_PKR, /* pkr */
-+ IA64_PMC, /* pmc */
-+ IA64_PMD, /* pmd */
-+ IA64_RR /* rr */
-+};
-+
-+/* instruction type */
-+enum {
-+ IA64_INST_TPA=1,
-+ IA64_INST_TAK
-+};
-+
-+/* Generate Mask
-+ * Parameter:
-+ * bit -- starting bit
-+ * len -- how many bits
-+ */
-+#define MASK(bit,len) \
-+({ \
-+ __u64 ret; \
-+ \
-+ __asm __volatile("dep %0=-1, r0, %1, %2" \
-+ : "=r" (ret): \
-+ "M" (bit), \
-+ "M" (len) ); \
-+ ret; \
-+})
-+
-+#endif // CONFIG_VTI
-+
/*
* CPU type, hardware bug flags, and per-CPU state. Frequently used
- * state comes earlier:
-@@ -408,12 +565,16 @@
+@@ -408,12 +413,14 @@
*/
/* Return TRUE if task T owns the fph partition of the CPU we're running on. */
-+#ifdef XEN
-+#define ia64_is_local_fpu_owner(t) 0
-+#else
++#ifndef XEN
#define ia64_is_local_fpu_owner(t) \
({ \
struct task_struct *__ia64_islfo_task = (t); \
---- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/system.h 2005-03-01 23:38:07.000000000 -0800
-+++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/system.h 2005-05-18 12:40:50.000000000 -0700
-@@ -24,8 +24,22 @@
+--- /home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/system.h 2005-03-01 23:38:07.000000000 -0800
++++ /home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/system.h 2005-05-20 09:36:02.000000000 -0700
+@@ -18,14 +18,19 @@
+ #include <asm/page.h>
+ #include <asm/pal.h>
+ #include <asm/percpu.h>
++#ifdef XEN
++#include <asm/xensystem.h>
++#endif
+
+ #define GATE_ADDR __IA64_UL_CONST(0xa000000000000000)
+ /*
* 0xa000000000000000+2*PERCPU_PAGE_SIZE
* - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
*/
-+#ifdef XEN
-+#ifdef CONFIG_VTI
-+#define XEN_VIRT_SPACE_LOW 0xe800000000000000
-+#define XEN_VIRT_SPACE_HIGH 0xf800000000000000
-+/* This is address to mapping rr7 switch stub, in region 5 */
-+#define XEN_RR7_SWITCH_STUB 0xb700000000000000
-+#endif // CONFIG_VTI
-+
-+#define KERNEL_START 0xf000000004000000
-+#define PERCPU_ADDR 0xf100000000000000-PERCPU_PAGE_SIZE
-+#define SHAREDINFO_ADDR 0xf100000000000000
-+#define VHPT_ADDR 0xf200000000000000
-+#else
++#ifndef XEN
#define KERNEL_START __IA64_UL_CONST(0xa000000100000000)
#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
+#endif
#ifndef __ASSEMBLY__
-@@ -205,6 +219,9 @@
- * ia64_ret_from_syscall_clear_r8.
- */
- extern struct task_struct *ia64_switch_to (void *next_task);
-+#ifdef CONFIG_VTI
-+extern struct task_struct *vmx_ia64_switch_to (void *next_task);
-+#endif // CONFIG_VTI
-
- struct task_struct;
-
-@@ -218,10 +235,32 @@
+@@ -218,6 +223,7 @@
# define PERFMON_IS_SYSWIDE() (0)
#endif
-+#ifdef XEN
-+#define IA64_HAS_EXTRA_STATE(t) 0
-+#else
++#ifndef XEN
#define IA64_HAS_EXTRA_STATE(t) \
((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
|| IS_IA32_PROCESS(ia64_task_regs(t)) || PERFMON_IS_SYSWIDE())
-+#endif
-
-+#ifdef CONFIG_VTI
-+#define __switch_to(prev,next,last) do { \
-+ if (VMX_DOMAIN(prev)) \
-+ vmx_save_state(prev); \
-+ else { \
-+ if (IA64_HAS_EXTRA_STATE(prev)) \
-+ ia64_save_extra(prev); \
-+ } \
-+ if (VMX_DOMAIN(next)) \
-+ vmx_load_state(next); \
-+ else { \
-+ if (IA64_HAS_EXTRA_STATE(next)) \
-+ ia64_save_extra(next); \
-+ } \
-+ ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
-+ (last) = vmx_ia64_switch_to((next)); \
-+} while (0)
-+#else // CONFIG_VTI
- #define __switch_to(prev,next,last) do { \
- if (IA64_HAS_EXTRA_STATE(prev)) \
- ia64_save_extra(prev); \
-@@ -230,6 +269,7 @@
+@@ -230,6 +236,7 @@
ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
(last) = ia64_switch_to((next)); \
} while (0)
-+#endif // CONFIG_VTI
++#endif
#ifdef CONFIG_SMP
/*
#include <asm/vmmu.h>
#include <public/arch-ia64.h>
#include <asm/vmx_phy_mode.h>
+#include <asm/vmx.h>
/* Global flag to identify whether Intel vmx feature is on */
u32 vmx_enabled = 0;
__vsa_base = tmp_base;
else
ASSERT(tmp_base != __vsa_base);
+
+ /* Init stub for rr7 switch */
+ vmx_init_double_mapping_stub();
}
typedef union {
panic("ia64_pal_vp_create failed. \n");
}
+void vmx_init_double_mapping_stub(void)
+{
+ u64 base, psr;
+ extern void vmx_switch_rr7(void);
+
+ base = (u64) &vmx_switch_rr7;
+ base = *((u64*)base);
+
+ psr = ia64_clear_ic();
+ ia64_itr(0x1, IA64_TR_RR7_SWITCH_STUB, XEN_RR7_SWITCH_STUB,
+ pte_val(pfn_pte(__pa(base) >> PAGE_SHIFT, PAGE_KERNEL)),
+ RR7_SWITCH_SHIFT);
+ ia64_set_psr(psr);
+ ia64_srlz_i();
+ printk("Add TR mapping for rr7 switch stub, with physical: 0x%lx\n", (u64)(__pa(base)));
+}
+
/* Other non-context related tasks can be done in context switch */
void
vmx_save_state(struct exec_domain *ed)
efi_memmap_walk(find_max_pfn, &max_page);
printf("find_memory: efi_memmap_walk returns max_page=%lx\n",max_page);
-#ifdef CONFIG_VTI
- /* Only support up to 64G physical memory by far */
- if (max_page > (0x1000000000UL / PAGE_SIZE))
- panic("Not suppport memory larger than 16G\n");
-#endif // CONFIG_VTI
-
heap_start = memguard_init(ia64_imva(&_end));
printf("Before heap_start: 0x%lx\n", heap_start);
heap_start = __va(init_boot_allocator(__pa(heap_start)));
#ifndef _ASM_IA64_VT_H
#define _ASM_IA64_VT_H
+#define RR7_SWITCH_SHIFT 12 /* 4k enough */
+
extern void identify_vmx_feature(void);
extern unsigned int vmx_enabled;
extern void vmx_init_env(void);
extern void vmx_final_setup_domain(struct domain *d);
+extern void vmx_init_double_mapping_stub(void);
extern void vmx_save_state(struct exec_domain *ed);
extern void vmx_load_state(struct exec_domain *ed);
extern vmx_insert_double_mapping(u64,u64,u64,u64,u64);
--- /dev/null
+#ifndef _ASM_IA64_XENPROCESSOR_H
+#define _ASM_IA64_XENPROCESSOR_H
+/*
+ * xen specific processor definition
+ *
+ * Copyright (C) 2005 Hewlett-Packard Co.
+ * Dan Magenheimer (dan.magenheimer@hp.com)
+ *
+ * Copyright (C) 2005 Intel Co.
+ * Kun Tian (Kevin Tian) <kevin.tian@intel.com>
+ *
+ */
+
+
+#define ia64_is_local_fpu_owner(t) 0
+
+/* like above but expressed as bitfields for more efficient access: */
+struct ia64_psr {
+ __u64 reserved0 : 1;
+ __u64 be : 1;
+ __u64 up : 1;
+ __u64 ac : 1;
+ __u64 mfl : 1;
+ __u64 mfh : 1;
+ __u64 reserved1 : 7;
+ __u64 ic : 1;
+ __u64 i : 1;
+ __u64 pk : 1;
+ __u64 reserved2 : 1;
+ __u64 dt : 1;
+ __u64 dfl : 1;
+ __u64 dfh : 1;
+ __u64 sp : 1;
+ __u64 pp : 1;
+ __u64 di : 1;
+ __u64 si : 1;
+ __u64 db : 1;
+ __u64 lp : 1;
+ __u64 tb : 1;
+ __u64 rt : 1;
+ __u64 reserved3 : 4;
+ __u64 cpl : 2;
+ __u64 is : 1;
+ __u64 mc : 1;
+ __u64 it : 1;
+ __u64 id : 1;
+ __u64 da : 1;
+ __u64 dd : 1;
+ __u64 ss : 1;
+ __u64 ri : 2;
+ __u64 ed : 1;
+ __u64 bn : 1;
+#ifdef CONFIG_VTI
+ __u64 ia : 1;
+ __u64 vm : 1;
+ __u64 reserved5 : 17;
+#else // CONFIG_VTI
+ __u64 reserved4 : 19;
+#endif // CONFIG_VTI
+};
+
+#ifdef CONFIG_VTI
+/* vmx like above but expressed as bitfields for more efficient access: */
+typedef union{
+ __u64 val;
+ struct{
+ __u64 reserved0 : 1;
+ __u64 be : 1;
+ __u64 up : 1;
+ __u64 ac : 1;
+ __u64 mfl : 1;
+ __u64 mfh : 1;
+ __u64 reserved1 : 7;
+ __u64 ic : 1;
+ __u64 i : 1;
+ __u64 pk : 1;
+ __u64 reserved2 : 1;
+ __u64 dt : 1;
+ __u64 dfl : 1;
+ __u64 dfh : 1;
+ __u64 sp : 1;
+ __u64 pp : 1;
+ __u64 di : 1;
+ __u64 si : 1;
+ __u64 db : 1;
+ __u64 lp : 1;
+ __u64 tb : 1;
+ __u64 rt : 1;
+ __u64 reserved3 : 4;
+ __u64 cpl : 2;
+ __u64 is : 1;
+ __u64 mc : 1;
+ __u64 it : 1;
+ __u64 id : 1;
+ __u64 da : 1;
+ __u64 dd : 1;
+ __u64 ss : 1;
+ __u64 ri : 2;
+ __u64 ed : 1;
+ __u64 bn : 1;
+ __u64 reserved4 : 19;
+ };
+} IA64_PSR;
+
+typedef union {
+ __u64 val;
+ struct {
+ __u64 code : 16;
+ __u64 vector : 8;
+ __u64 reserved1 : 8;
+ __u64 x : 1;
+ __u64 w : 1;
+ __u64 r : 1;
+ __u64 na : 1;
+ __u64 sp : 1;
+ __u64 rs : 1;
+ __u64 ir : 1;
+ __u64 ni : 1;
+ __u64 so : 1;
+ __u64 ei : 2;
+ __u64 ed : 1;
+ __u64 reserved2 : 20;
+ };
+} ISR;
+
+
+typedef union {
+ __u64 val;
+ struct {
+ __u64 ve : 1;
+ __u64 reserved0 : 1;
+ __u64 size : 6;
+ __u64 vf : 1;
+ __u64 reserved1 : 6;
+ __u64 base : 49;
+ };
+} PTA;
+
+typedef union {
+ __u64 val;
+ struct {
+ __u64 rv : 16;
+ __u64 eid : 8;
+ __u64 id : 8;
+ __u64 ig : 32;
+ };
+} LID;
+
+typedef union{
+ __u64 val;
+ struct {
+ __u64 rv : 3;
+ __u64 ir : 1;
+ __u64 eid : 8;
+ __u64 id : 8;
+ __u64 ib_base : 44;
+ };
+} ipi_a_t;
+
+typedef union{
+ __u64 val;
+ struct {
+ __u64 vector : 8;
+ __u64 dm : 3;
+ __u64 ig : 53;
+ };
+} ipi_d_t;
+
+
+#define IA64_ISR_CODE_MASK0 0xf
+#define IA64_UNIMPL_DADDR_FAULT 0x30
+#define IA64_UNIMPL_IADDR_TRAP 0x10
+#define IA64_RESERVED_REG_FAULT 0x30
+#define IA64_REG_NAT_CONSUMPTION_FAULT 0x10
+#define IA64_NAT_CONSUMPTION_FAULT 0x20
+#define IA64_PRIV_OP_FAULT 0x10
+
+/* indirect register type */
+enum {
+ IA64_CPUID, /* cpuid */
+ IA64_DBR, /* dbr */
+ IA64_IBR, /* ibr */
+ IA64_PKR, /* pkr */
+ IA64_PMC, /* pmc */
+ IA64_PMD, /* pmd */
+ IA64_RR /* rr */
+};
+
+/* instruction type */
+enum {
+ IA64_INST_TPA=1,
+ IA64_INST_TAK
+};
+
+/* Generate Mask
+ * Parameter:
+ * bit -- starting bit
+ * len -- how many bits
+ */
+#define MASK(bit,len) \
+({ \
+ __u64 ret; \
+ \
+ __asm __volatile("dep %0=-1, r0, %1, %2" \
+ : "=r" (ret): \
+ "M" (bit), \
+ "M" (len) ); \
+ ret; \
+})
+
+#endif // CONFIG_VTI
+
+#endif // _ASM_IA64_XENPROCESSOR_H
--- /dev/null
+#ifndef _ASM_IA64_XENSYSTEM_H
+#define _ASM_IA64_XENSYSTEM_H
+/*
+ * xen specific context definition
+ *
+ * Copyright (C) 2005 Hewlett-Packard Co.
+ * Dan Magenheimer (dan.magenheimer@hp.com)
+ *
+ * Copyright (C) 2005 Intel Co.
+ * Kun Tian (Kevin Tian) <kevin.tian@intel.com>
+ *
+ */
+#include <asm/config.h>
+#include <linux/kernel.h>
+
+/* Define HV space hierarchy */
+#ifdef CONFIG_VTI
+#define XEN_VIRT_SPACE_LOW 0xe800000000000000
+#define XEN_VIRT_SPACE_HIGH 0xf800000000000000
+/* This is address to mapping rr7 switch stub, in region 5 */
+#define XEN_RR7_SWITCH_STUB 0xb700000000000000
+#endif // CONFIG_VTI
+
+#define KERNEL_START 0xf000000004000000
+#define PERCPU_ADDR 0xf100000000000000-PERCPU_PAGE_SIZE
+#define SHAREDINFO_ADDR 0xf100000000000000
+#define VHPT_ADDR 0xf200000000000000
+
+#ifndef __ASSEMBLY__
+
+#define IA64_HAS_EXTRA_STATE(t) 0
+
+#ifdef CONFIG_VTI
+extern struct task_struct *vmx_ia64_switch_to (void *next_task);
+#define __switch_to(prev,next,last) do { \
+ if (VMX_DOMAIN(prev)) \
+ vmx_save_state(prev); \
+ else { \
+ if (IA64_HAS_EXTRA_STATE(prev)) \
+ ia64_save_extra(prev); \
+ } \
+ if (VMX_DOMAIN(next)) \
+ vmx_load_state(next); \
+ else { \
+ if (IA64_HAS_EXTRA_STATE(next)) \
+ ia64_save_extra(next); \
+ } \
+ ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
+ (last) = vmx_ia64_switch_to((next)); \
+} while (0)
+#else // CONFIG_VTI
+#define __switch_to(prev,next,last) do { \
+ if (IA64_HAS_EXTRA_STATE(prev)) \
+ ia64_save_extra(prev); \
+ if (IA64_HAS_EXTRA_STATE(next)) \
+ ia64_load_extra(next); \
+ ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
+ (last) = ia64_switch_to((next)); \
+} while (0)
+#endif // CONFIG_VTI
+
+#endif // __ASSEMBLY__
+#endif // _ASM_IA64_XENSYSTEM_H
projects / xen.git / commitdiff